An Efficient Implementation Of Aes On Fpga

An Efficient Implementation Of Aes On Fpga

AN EFFICIENT IMPLEMENTATION OF AES ON FPGA



Author name:A.MONIGHA Author name:Mr.G.YUVARAJ

Dept. name of organization: Dept. name of organization:

M.E (VLSI ),dept of ECE Assistant professor,dept of ECE

Name of organization:VCEW Name of organiosation:VCEW

City, Country: Elayampalayam,India City,Country:Elayampalayam,India



monigha1priya@gmail.com engineer.yuvaraja@gmail.com Abstract– Speed and area reduction are one of the major issues in VLSI applications. An implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. The design uses looping method will reduce area and increase the speed .By using encrypted round for speed and pipelining ,isomorphic mapping method for area.This algorithm achieves efficiency and high throughput.



Keywords–––– Advanced Encryption Standard(AES) ,AaSP , fine grained,many core, synchronous dataflow



I.INTRODUCTION

Now–a–days security plays a vital role in eletronics world.The speed and area optimization is an important issue in today's electronics.The AES is a cryptographic algorithm that is used to protect electronic data or information. AES algorithm is a symmetric key used in that can encrypt and decrypt

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